Keysight Technologies is heading to DesignCon 2026 with a clear message: if AI systems are pushing the physical limits of silicon, interconnects, and memory, test and validation need to move even faster.
At Booth 1039 in the Santa Clara Convention Center (Feb. 24‑26), the company will showcase a broad portfolio of end‑to‑end solutions designed to help engineers de‑risk AI infrastructure early—from advanced packaging and chiplets to PCIe 7.0 and 1.6T networking fabrics.
The throughline across its demos? Ensuring that bleeding‑edge AI designs don’t just work in simulation, but scale reliably at system level.
From Chiplets to 3D ICs: Designing for AI at the Package Level
As AI accelerators evolve toward multi‑die architectures, chiplet and 3D IC integration have become central to performance scaling. Keysight’s Chiplet 3D Interconnect Designer demo walks through a workflow aimed at accelerating multi‑die interconnect development for AI and high‑performance computing devices.
With chiplets now a mainstream strategy for improving yield and modularity, validating die‑to‑die communication paths early is critical. Keysight is positioning its tools to help engineers model, test, and refine those connections before they become costly bottlenecks in production silicon.
Signal Integrity at 3.2T Speeds
AI infrastructure isn’t just about compute—it’s about moving massive amounts of data without loss.
Keysight’s signal integrity demo pairs its Physical Layer Test System (PLTS2026) with the NA5307A 250 GHz Frequency Extender to demonstrate the bandwidth and measurement precision required for next‑generation infrastructure validation.
At speeds approaching 3.2 T‑class environments, even minor signal degradation can cascade into performance failures. By showcasing high‑frequency characterization tools, Keysight is targeting the growing need for ultra‑wideband validation in hyperscale and AI data‑center deployments.
Memory Under Pressure: DDR5 and GDDR7
AI workloads are notoriously memory‑hungry, and the company’s memory validation demos reflect that pressure.
Keysight will run a live DDR5 system for mainstream electrical validation, alongside a GDDR7 PAM3 signal integrity setup powered by its new SNDR (Signal‑to‑Noise‑and‑Distortion Ratio) and jitter measurement suite.
As memory standards evolve toward higher speeds and new modulation schemes, compliance testing becomes increasingly complex. Keysight’s approach aims to streamline both validation and debug, shortening time to market for AI‑optimized memory subsystems.
PCIe 7.0 and PAM4: Debugging at the PHY and Protocol Layer
PCIe continues to anchor AI accelerator connectivity, and with PCIe 7.0 on the horizon, electrical and protocol‑layer validation is intensifying.
Keysight’s demo highlights next‑gen PCIe test solutions spanning both PHY and protocol layers. The setup features the UXR‑Series oscilloscope, M8050A BERT platform, and dedicated PCIe test software to accelerate debug, enhance margin analysis, and improve link reliability.
For AI system architects, ensuring that high‑speed serial links remain stable under real‑world workloads is increasingly mission‑critical. A marginal PCIe link can undermine entire accelerator clusters.
448 Gbps and Beyond: Pathfinding for Future Interconnects
Looking further ahead, Keysight will demonstrate its 448 Gbps Pathfinding solution, leveraging the M8199B arbitrary waveform generator and N1046A electrical channel module.
The goal: enable researchers to generate and analyze advanced modulation schemes, including PAM4, PAM6, and PAM8, to evaluate signaling trade‑offs for next‑generation interconnect architectures.
As data rates climb, modulation complexity increases—and so does the risk of signal‑integrity breakdown. Keysight’s tools are aimed squarely at researchers and early adopters shaping the next wave of AI networking standards.
1.6T Interconnect Benchmarking for AI Networks
Perhaps the headline demo is Keysight’s focus on 1.6 T interconnects, a critical milestone for AI cluster scaling.
The company will showcase how its INPT‑1600GE benchtop test system validates bit error rate (BER) and forward error correction (FEC), measures link quality, and benchmarks AI workloads at 1.6 T‑class speeds.
As AI training clusters expand into thousands of GPUs and custom accelerators, network performance becomes a gating factor. Validating throughput, reliability, and interoperability at these speeds is no longer optional—it’s foundational.
UALink and Scale‑Up Ethernet for AI Infrastructure
Keysight will also spotlight automation and compliance solutions for UALink and scale‑up Ethernet, emerging as key connectivity frameworks for AI infrastructure.
The demos focus on automated test workflows, expanded measurement coverage, and streamlined calibration processes for 1.6 T‑class electrical networking interfaces. The aim is to reduce manual overhead while increasing conformance confidence.
In an environment where AI fabrics are rapidly evolving, interoperability validation can make or break deployment timelines.
Beyond the Booth
In addition to live demonstrations, Keysight will participate in 16 paper, panel, and tutorial presentations at DesignCon, along with nine talks during the Keysight Educational Forum on February 25 in the Great America K Ballroom.
That heavy presence underscores the company’s strategy: position itself not just as a test equipment vendor, but as a technical partner embedded in the standards and research conversations shaping AI hardware’s future.
Why It Matters
AI system performance is no longer limited by compute alone. Interconnect bandwidth, memory throughput, packaging density, and compliance validation are now equally critical.
As hyperscalers and semiconductor vendors race toward 1.6 T networking and advanced chiplet architectures, early‑stage validation becomes a competitive differentiator. The faster teams can de‑risk physical constraints and interoperability issues, the sooner AI systems can scale from lab prototypes to production clusters.
At DesignCon 2026, Keysight is making its case that the road to scalable AI runs straight through the test bench.
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